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Abstract: Caches enhance the performance of multiprocessors by reducing network traffic and average memory access latency. However, cache-based systems must address the problem of cache coherence. We propose the LimitLESS directory protocol to solve this problem. The LimitLESS scheme uses a combination of hardware and software techniques to realize the performance of a full-map directory with the memory overhead of a limited directory. This protocol is supported by Alewife, a large-scale multiprocessor.... (Update)
Context of citations to this paper: More
...the data reference status, and to invalidate or update cached copies. Snoopy buses [12, 15, 29, 35, 38] and memory directories [2, 4, 5, 14, 37] are two prominent hardware coherence mechanisms. With run time interproces2 sor dataflow information, the coherence hardware...
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BibTeX entry: (Update)
David Chaiken, John Kubiatowicz, and Anant Agarwal. LimitLESS Directories: A Scalable Cache Coherence Scheme. In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 224--234. ACM, April 1991. http://citeseer.ist.psu.edu/article/chaiken91limitless.html More
@inproceedings{ chaiken91limitless,
author = "D. Chaiken and J. Kubiatowics and A. Agarwal",
title = "Limit{LESS} Directories: {A} Scalable Cache Coherence Scheme",
booktitle = "Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating System ({ASPLOS})",
journal = "SIGPLAN Notices",
volume = "26",
number = "4",
publisher = "ACM Press",
address = "New York, NY",
isbn = "0-89791-380-9",
pages = "224--234",
year = "1991",
url = "citeseer.ist.psu.edu/article/chaiken91limitless.html" }
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213 Weak Ordering - A New Definition - Adve, Hill - 1990
212 APRIL: A Processor Architecture for Multiprocessing - Agarwal, Lim et al. - 1990
195 A New Solution to Coherence Problems in Multicache Systems (context) - Censier, Feautrier - 1978
156 An Evaluation of Directory Schemes for Cache Coherence - Agarwal, Simoni et al. - 1988
122 Firefly: a Multiprocessor Workstation (context) - Thacker, Stewart - 1987
113 Directory-Based Cache-Coherence in Large-Scale Multiprocesso.. (context) - Chaiken, Fields et al. - 1990
111 Using Cache Memory to Reduce Processor-Memory Traffic (context) - Goodman - 1983
99 Adaptive Software Cache Management for Distributed Shared Me.. - Bennett, Carter et al. - 1990
82 A LowOverhead Coherence Solution for Multiprocessors with Pr.. (context) - Papamarcos, Patel - 1985
66 A HighPerformance Parallel Lisp (context) - Kranz, Halstead et al. - 1989
66 Implementing a Cache Consistency Protocol (context) - Katz, Eggers et al. - 1985
53 A VLSI Architecture for Concurrent Data Structures (context) - Dally - 1987
49 An Economical Solution to the Cache Coherence Problem (context) - Archibald, Baer - 1985
48 and Event Ordering in Multiprocessors (context) - Dubois, Scheurich et al. - 1988
43 Software-Controlled Caches in the VMP Multiprocessor (context) - Cheriton, Slavenberg et al. - 1986
37 Concurrent VLSI Architectures (context) - Seitz - 1984
36 An Empirical Evaluation of Two Memory-Efficient Directory Me.. (context) - O'Krafka, Newton - 1990
32 Cache Design in the Tightly Coupled Multiprocessor System (context) - Tang - 1976
23 Distributed-Directory Scheme: Scalable Coherent Interface (context) - James, Laundrie et al. - 1990
18 Analysis of Cache Invalidation Patterns in Multiprocessors (context) - Weber, Gupta - 1989
17 SUN Microsystems (context) - Manual - 1988
5 A study of backoff barrier synchronization in shared-memory .. (context) - Cherian - 1989
3 Latency Tolerance in Large-Scale Multiprocessors (context) - Kurihara, Chaiken et al. - 1990
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