Design Considerations for Low-Power, High-Speed CMOS Analog/Digital Converters [1 citations — 0 self]
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by Thomas B. Cho, David W. Cline, Cormac S. G. Conroy, Paul R. Gray
http://kabuki.eecs.berkeley.edu/~tcho/LowPwrSymp94.ps
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Abstract:
This paper reviews architectural and circuit design considerations for realization of low power dissipation in high-speed CMOS A/D converters. Basic limitations on achievable power dissipation in MOS samplers and quantizers is first discussed. Then a number of practical design aspects are illustrated with discussion of a 10-bit, 20-Msample/s pipeline A/D converter[1] implemented in 1.2-��m CMOS technology which achieves a power dissipation of 35 mW at full speed operation on a 3.3V power supply.
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