Interconnect performance estimation models for synthesis and design planning (1998) [8 citations — 3 self]

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by Jason Cong, Zhigang Pan

in IEEE/ACM Int. Workshop on Logic Synthesis

http://cadlab.cs.ucla.edu/~cong/papers/iwls98_estimation.ps.gz

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@INPROCEEDINGS{Cong98interconnectperformance,
    author = {Jason Cong and Zhigang Pan},
    title = {Interconnect performance estimation models for synthesis and design planning},
    booktitle = {in IEEE/ACM Int. Workshop on Logic Synthesis},
    year = {1998},
    pages = {427--433}
}

Abstract:

The objective of this work is to provide simple, efficient, yet reasonably accurate interconnect performance estimation models for synthesis and design planning under various complex interconnect optimization techniques. We have developed a set of closed-form delay estimation models as functions of interconnect length as well as some other key interconnect and device parameters with the consideration of various interconnect optimization techniques, which include optimal wire-sizing (OWS), simultaneous driver and wire sizing (SDWS), and simultaneous buffer insertion/sizing and wire sizing (BISWS). These models have been tested on a wide range of parameters and shown to have about 90 % accuracy on average when compared with the delays obtained by running complex optimization algorithms directly followed by HSPICE simulations. Moreover, our models run in constant time for all practical purposes. As a result, these simple, fast, yet accurate models are expected to be very useful for a wide variety of purposes, including layout-driven logic and high level synthesis, performance-driven floorplanning, and interconnect planning. 1.

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