Beng-Hong Lim, Ricardo Bianchini  Home/Search
Context Related
Links: ACM DBLP | mit.edu/bhlim/lathide/paper.ps.gz Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: mit.edu (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: The performance benefits of multithreading and software prefetching depend heavily on hardware and application-specific parameters, such as the multiprocessor's remote memory access latency and the cache miss rate of parallel applications. This paper considers the relationship between these parameters and the maximum performance improvement achievable through multithreading and software prefetching. Specifically, the paper presents new analytical models and experimental measurements of several... (Update)
Context of citations to this paper: More
...of elapsed times. Combined multithreading and prefetching was also the subject of a study in the area of microprocessors [Lim and Bianchini, 1996]. The implementation on the MIT Alewife Machine showed that only a few of the applications can benefit significantly from...
...delay. The first technique is multi threading. Multi threading has been used in many systems to mask communication costs [17, 20, 28]. The difference here is that notification delay may be many times larger than the base communication costs, and therefore multi...
Cited by: More
Exploiting Thread-Level Parallelism On . . . - Lo (1998) (Correct)
Hardware and Software Mechanisms for Multithreading in.. - Bradford (2001) (Correct)
An Asynchronous Protocol for Release Consistent Distributed.. - Yeo, Yeom, Park (Correct)
Similar documents (at the sentence level):
38.1%: Evaluating the Performance of Multithreading and Prefetching.. - Bianchini, Lim (1996) (Correct)
35.0%: Limits on the Performance Benefits of Multithreading and.. - Lim, Bianchini (1996) (Correct)
Active bibliography (related documents): More All
0.2: General Informations - Most Of The (Correct)
0.1: Simultaneous Multithreading: Maximizing On-Chip Parallelism - Tullsen, Eggers, Levy (1995) (Correct)
0.1: Balanced Multithreading: Increasing Throughput via a.. - Tune, Kumar, Tullsen, .. (2004) (Correct)
Similar documents based on text: More All
0.2: Analysis of the Effectiveness of Multithreading for.. - Pattery, Lee, Won (2002) (Correct)
0.1: Nomad: A Scalable Operating System for Clusters of Uni and.. - Pinheiro, Bianchini (2000) (Correct)
0.1: Efficiently Adapting to Sharing Patterns in Software DSMs - Monnerat, Bianchini (1998) (Correct)
Related documents from co-citation: More All
4: the ACM SIGMOD Int (context) - of - 1993
3: Multi-threading and remote latency in software dsms - Thitikamol, Keleher - 1997
3: on Very Large Data Bases (context) - the, Inter - 1989
BibTeX entry: (Update)
Lim, B.-H. and R. Bianchini. "Limits on the Performance Benefits of Multithreading and Prefetching" in Proceedings of the International Conference on the Measurement and Modeling of Computer Systems. 1996. http://citeseer.ist.psu.edu/article/lim95limits.html More
@inproceedings{ lim96limits,
author = "Beng-Hong Lim and Ricardo Bianchini",
title = "Limits on the Performance Benefits of Multithreading and Prefetching",
booktitle = "Measurement and Modeling of Computer Systems",
pages = "37-46",
year = "1996",
url = "citeseer.ist.psu.edu/article/lim95limits.html" }
Citations (may not include all citations):496 SPLASH: Stanford Parallel Applications for Shared-Memory (context) - Singh, Weber et al. - 1992 ACM
478 The Stanford DASH Multiprocessor (context) - Lenoski, Laudon et al. - 1992 ACM DBLP
358 The Tera Computer System - Alverson, Callahan et al. - 1990 ACM DBLP
249 Tolerating Latency Through Software-Controlled Prefetching i.. - Mowry, Gupta - 1991
217 NASA Ames Research Center (context) - Bailey, Parallel et al. - 1994
212 The MIT Alewife Machine: Architecture and Performance - Agarwal, Bianchini et al. - 1995 DBLP
170 LimitLESS Directories: A Scalable Cache Coherence Scheme - Chaiken, Kubiatowicz et al. - 1991 ACM DBLP
157 Architecture and Applications of the HEP Multiprocessor Comp.. (context) - Smith - 1981
149 Software Prefetching (context) - Callahan, Kennedy et al. - 1991 ACM DBLP
137 Lockup-Free Instruction Fetch/Prefetch Cache Organization (context) - Kroft - 1981
121 Monsoon: An Explicit Token-Store Architecture (context) - Papadopoulos, Culler - 1990
109 Comparative Evaluation of Latency Reducing and Tolerating Te.. - Gupta, Hennessy et al. - 1991
101 IEEE Transactions on Parallel and Distributed Systems (context) - Agarwal, in - 1992
53 Processor Coupling: Integrating Compile Time and Runtime Sch.. - Keckler, Dally - 1992 DBLP
49 Sequential Hardware Prefetching in Shared-Memory Multiproces.. (context) - Dahlgren, Dubois et al. - 1995 ACM DBLP
47 Sparcle: An Evolutionary Processor Design for Multiprocessor.. (context) - Agarwal, Kubiatowicz et al. - 1993
44 Analysis of Multithreaded Architectures for Parallel Computi.. (context) - Saavedra-Barrera, Culler et al. - 1990
40 Interleaving: A Multithreading Technique Targeting Multiproc.. - Laudon, Gupta et al. - 1994
35 The KSR1: Bridging the Gap Between Shared Memory and MPPs (context) - Frank, Rothnie - 1993
33 Register Relocation: Flexible Contexts for Multithreading - Waldspurger, Weihl - 1993
28 Closing the Window of Vulnerability in Multiphase Memory Tra.. - Kubiatowicz, Chaiken et al. - 1992 ACM DBLP
23 The Effectiveness of Multiple Hardware Contexts - Thekkath, Eggers - 1994 ACM DBLP
19 Cray Research (context) - Architecture - 1993
17 Multithreaded Computer Architecture - A Summary of the State.. (context) - Iannucci - 1994
10 Multithreaded Processor Architectures (context) - Byrd, Holliday - 1995 ACM
4 The Multi-Threaded Architecture Multiprocessor - Hum - 1994
3 Analysis of Multithreaded Architectures with Distributed Sha.. (context) - Nemawarkar, Govindarajan et al. - 1993
1 A Performance Study of Software and Hardware Prefetching Sch.. (context) - Chen, Baer - 1994
1 A Preliminary Evaluation of Cache-MissInitiated Prefetching .. (context) - Bianchini, LeBlanc - 1994
Documents on the same site (http://fermivista.math.jussieu.fr/ftp/ftp.cag.lcs.mit.edu.html): More
Reactive Synchronization Algorithms for Multiprocessors - Lim (1994) (Correct)
MGS: A Multigrain Shared Memory System - Yeung (1996) (Correct)
Dribbling Registers: A Mechanism for Reducing Context.. - Vijayaraghavan.. (1992) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC